1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register for use as a scanning-line driving circuit for an image display apparatus or the like, which is formed by field effect transistors of the same conductivity type only.
2. Description of the Background Art
An image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display includes a display panel with a plurality of pixels arrayed in a matrix. A gate line (scanning line) is provided for each row of pixels (pixel line), and gate lines are sequentially selected and driven in a cycle of one horizontal period of a display signal, so that a displayed image is updated. As a gate-line driving circuit (scanning-line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register for performing a shift operation that makes a round in one frame period of a display signal can be used.
To reduce the number of steps in the manufacturing process of a display apparatus, such shift register used as the gate-line driving circuit is preferably formed by field effect transistors of the same conductivity type only. Accordingly, various types of shift registers formed by N- or P-type field effect transistors only and display apparatus containing such shift registers have been proposed (e.g., Japanese Patent Application Laid-Open Nos. 2004-246358 and 2006-24350). As a field effect transistor, a metal-oxide-semiconductor (MOS) transistor, a thin film transistor (TFT), or the like is used.
A shift register used for the gate-line driving circuit is formed of a plurality of shift registers provided for each pixel line, i.e., each gate line connected in cascade (cascade-connected). For ease of description, each of a plurality of shift registers constituting the gate-line driving circuit will be called “a unit shift register” throughout the present specification.
A typical unit shift register includes, in the output stage, an output pull-up transistor (pull-up MOS transistor Q1) connected between an output terminal (first gate voltage signal terminal GOUT in the aforementioned JP2004-246358) and a clock terminal (first power clock CKV) and an output pull-down transistor (pull-down MOS transistor Q2) connected between the output terminal and a reference voltage terminal (gate-off voltage terminal VOFF).
In such shift register, the output pull-up transistor is turned on and the output pull-down transistor is turned off in response to a predetermined input signal (output signal GOUT [N−1] from a preceding stage), and a clock signal input to the clock terminal in this mode is transmitted to the output terminal, and an output signal is then output. During a period in which the above-mentioned input signal is not input, the output pull-up transistor turns off and the output pull-down transistor turns on, so that the voltage level (hereinafter briefly called “level”) at the output terminal is kept at the L (low) level.
A display apparatus employing amorphous silicon TFTs (a-Si TFTs) as shift registers of a gate-line driving circuit easily achieves large-area display with great productivity, and is widely used as the screen of a notebook PC, a large-screen display apparatus, etc.
Conversely, an a-Si TFT tends to have its threshold voltage shifted in the positive direction when the gate electrode is continuously positive-biased (dc-biased), resulting in degraded driving capability (current-flowing capability). Particularly, a shift register of a gate-line driving circuit carries out an operation of positively dc-biasing the gate of the output pull-down transistor for about one frame period (about 16 ms), during which the output pull-down transistor is degraded in driving capability. Then, the output pull-down transistor cannot discharge unnecessary charges if supplied to the output terminal resulting from noise or the like, disadvantageously resulting in a malfunction of erroneous activation of gate lines. It has been found that similar problems occurs in an organic TFT, not only in a-Si TFT.
The unit shift register disclosed in the aforementioned JP2004-246358 swings its gate-to-source voltage in a certain cycle during a period in which the output pull-down transistor is on. This prevents the gate of the output pull-down transistor from being dc-biased, minimizing the shift in threshold voltage (which may also be called “Vth shift”) of the output pull-down transistor, which eliminates the aforementioned malfunction. To achieve such operation, the unit shift register disclosed in the aforementioned JP2004-246358 swings an output voltage of a power supply which charges the gate of the output pull-down transistor in a certain cycle.
A control device for a general-purpose gate-line driving circuit having conventionally been used (hereinafter referred to as “a driving control device”) does not have a power supply output that swings in a certain cycle. Therefore, a driving control unit meeting special specifications is necessary in order to achieve the technique disclosed in the aforementioned JP2004-246358, which arises concern for increased costs.
The aforementioned JP2006-24350 discloses a technique for minimizing the Vth shift of an output pull-down transistor (TdA) and the Vth shift of a transistor (T1A) which pulls down the gate electrode of an output pull-up transistor (Tu) in a unit shift register shown in FIG. 7. More specifically, a capacitive element (C2) is connected between a gate electrode node (Y) of these two pull-down transistors (TdA, T1A) and a clock terminal (CK1), and the voltage at the gate electrode node (Y) in a non-selected state of the shift register is swung by the coupling through the capacitive element (C2) in accordance with the level transition of clock signals. With this technique, the threshold voltage of the two pull-down transistors (TdA, T1A) finally comes close to an intermediate value between the H and L levels of the gate electrode node (Y) (when the clock signals have a duty ratio of 50%).
To increase the display quality of a display device, it is preferable that the gate line be stable in voltage in the non-selected state. It is therefore preferable that the resistance at the output node (output resistance) of the shift register connected to the gate line be low. The on-state resistance of the output pull-down transistor (TdA) is determined by the difference between its threshold voltage and H level of the gate electrode node (Y). In other words, as the difference between the threshold voltage and H level of the gate electrode node (Y) increases, the driving capability (current driving capability) of a transistor increases and the output resistance decreases.
In FIG. 7 of the aforementioned JP2006-24350, the potential at the H level of the gate electrode node (Y) of the output pull-down transistor (TdA) is determined by the relationship between the parasitic capacitance at the gate electrode node and the coupling capacitance of the aforementioned capacitive element (C2). As the parasitic capacitance decreases relative to the coupling capacitance, the potential at the H level can be increased. However, the output pull-down transistor (TdA) needs to have a certain channel width or larger in order to pull down the output terminal (OUT) with a low resistance, and the gate electrode node (Y) has a large parasitic capacitance. Therefore, to increase the potential at the H level of the gate electrode node (Y), the capacitive element (C2) needs to have a large capacitance, which, however, in turn increases the circuit area.